10 research outputs found

    A General Security Approach for Soft-information Decoding against Smart Bursty Jammers

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    Malicious attacks such as jamming can cause significant disruption or complete denial of service (DoS) to wireless communication protocols. Moreover, jamming devices are getting smarter, making them difficult to detect. Forward error correction, which adds redundancy to data, is commonly deployed to protect communications against the deleterious effects of channel noise. Soft-information error correction decoders obtain reliability information from the receiver to inform their decoding, but in the presence of a jammer such information is misleading and results in degraded error correction performance. As decoders assume noise occurs independently to each bit, a bursty jammer will lead to greater degradation in performance than a non-bursty one. Here we establish, however, that such temporal dependencies can aid inferences on which bits have been subjected to jamming, thus enabling counter-measures. In particular, we introduce a pre-decoding processing step that updates log-likelihood ratio (LLR) reliability information to reflect inferences in the presence of a jammer, enabling improved decoding performance for any soft detection decoder. The proposed method requires no alteration to the decoding algorithm. Simulation results show that the method correctly infers a significant proportion of jamming in any received frame. Results with one particular decoding algorithm, the recently introduced ORBGRAND, show that the proposed method reduces the block-error rate (BLER) by an order of magnitude for a selection of codes, and prevents complete DoS at the receiver.Comment: Accepted for GLOBECOM 2022 Workshops. Contains 7 pages and 7 figure

    Live demonstration: cyber attack against an ingestible medical device

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    Intelligent and compact healthcare systems are gaining interest, potentially changing medical monitoring and treatment procedures. Ingestible medical devices (IMD) inside a swallowable pill can transform unpleasant and immobile operations like endoscopy into a remote process. These devices raise a concern for security, where its absence can result in a lethal attack [1] . Some attacks have been shown on medical devices, such as insulin pumps and cardiac defibrillators [2] . A typical challenge for securing an IMD is its resource-constrained design. IMDs have to be small in size to make them swallowable, which limits the battery size. This obliges the device to run on ultra-low power, targeting hours of measurement and data transmission on a small battery. Considering that, it is generally not feasible to have calculation-intensive encryption or a separate cryptography core on the device. However, the security of an IMD is crucial as a breach can cause leakage of confidential data or a wrong diagnosis.ECCS-2128517 - National Science FoundationAccepted manuscrip

    A low-power dual-factor authentication unit for secure implantable devices

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    Abstract: This paper presents a dual-factor authentication protocol and its low-power implementation for security of implantable medical devices (IMDs). The protocol incorporates traditional cryptographic first-factor authentication using Datagram Transport Layer Security - Pre-Shared Key (DTLS-PSK) followed by the user's touch-based voluntary second-factor authentication for enhanced security. With a low-power compact always-on wake-up timer and touch-based wake-up circuitry, our test chip consumes only 735 pW idle state power at 20.15 Hz and 2.5 V. The hardware accelerated dual-factor authentication unit consumes 8 µW at 660 kHz and 0.87 V. Our test chip was coupled with commercial Bluetooth Low Energy (BLE) transceiver, DC-DC converter, touch sensor and coin cell battery to demonstrate standalone implantable operation and also tested using in-vitro measurement setup. ©2020 Paper presented at the 2020 IEEE Custom Integrated Circuits Conference (CICC 2020), March 22-25, 2020, Boston, Mass.Analog Devices Inc

    Multi-Code Multi-Rate Universal Maximum Likelihood Decoder using GRAND

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    We present the first fully-integrated universal Max- imum Likelihood decoder in 40 nm CMOS using the Guessing Random Additive Noise Decoding (GRAND) algorithm for low- power applications. The 0.83 mm2 multi-code multi-rate universal decoder can efficiently decode any code of length up to 128 bits with 1 μs latency at 68 MHz. Dynamic clock gating leveraging noise statistics reduces the average power dissipation to 3.75 mW at 1.1 V or 30.6 pJ/decoded bit with a throughput of 122.6 Mb/s. Universal decoding reduces hardware footprint, and the design allows seamless swapping between codebooks with no downtime, enabling use by multiple applications without switch-over
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